The present invention relates to a method of processing the output of a test tool and, in particular, to a method of processing the output of a HDL tool or the like. The present invention also relates to apparatus for processing the output of a tool.
Generally, integrated circuits (IC) are tested prior to their reduction to silicon. In this way, the overall development time for an integrated circuit can be reduced considerably. In practice, this means that an IC device can be brought to market more quickly. A number of test simulators are known which allow test departments to test how a device will function as soon as a preliminary design is completed. This can be prior to the reduction to silicon of the device.
When analyzing a circuit, the circuit is divided up into a number of smaller units, usually referred to as cells. Each cell will typically include a number of different components, such as gates, other logic elements or the like. Typically, an integrated circuit will comprise a large number of cells, such as many thousands or hundreds of thousands of cells.
To describe circuits on such a large scale, digital simulators have been developed. Numerous digital simulators have been developed to model the behavior of circuitry described using a hardware description language (HDL). HDL is a programming language which has been designed and optimized for simulating and thereby describing the behaviour of digital circuitry. HDL allows electrical aspects of circuit behaviour to be precisely described. In HDL, changes in a logic level trigger an evaluation of the effect.
HDL models typically provide a behavioural description of the circuitry of the designed device which can be synthesized into a net list which includes circuit diagrams of the device saved in textural form. In other words, the circuitry of the device is broken down into cells or small circuit portions, each of which has a known, behavior. These cells or small circuit portions are listed in the net list. Operation of the device is simulated by stimulating the net list by the application of a test bench. Test benches are HDL descriptions of circuit stimulus. The outputs of the cell in response to stimulus are compared with expected outputs to verify the, behavior of a circuit over time. The verification results may be analyzed to establish the circuit has functioned.
Most HDL simulators are able to generate output files which include the results of a simulation of a cell. The output files include information relating to individual elements of a cell. In particular, the files include waveforms. The waveforms, when viewed using the simulator are graphical representations of what the signals do over time. The information contained in the output files can be viewed by the user of the tool and compared with a reference set of information or other type of information. Included in a given file is all the information relating to a given cell. If the user of the tool wants to consider only part of a cell, it is difficult for the user to achieve this based on the files output by the tool
It is therefore an aim of embodiments of the present invention to address this difficulty.
According to a first aspect of the present invention there is provided a method of processing the output of a design tool, said output relating to a circuit under design, said method comprising the steps of selecting a part of said circuit: selecting information relating to each signal in the selected part of the circuit; and providing an output containing the selected information for the signals in the selected part of the circuit.
According to a second aspect of the present invention there is provided apparatus for processing the output of a design tool, said output relating to a circuit under design, said apparatus comprising means for defining a part of the circuit; means for selecting information for the signals in the selected part of the circuit; and means for providing an output containing the information relating to the selected signals.